The present invention relates to charge transfer devices; and more particularly, to charge transfer devices having an anti-blooming input structure.
Inherently, charge transfer devices can accommodate only very low currents. Specifically, the current handling capability of a very high speed charge transfer device is in the hundred microampere region; and generating such a low current level at high frequencies through high impedance lines is difficult, and susceptible to induced noise currents by capacitance coupling and leakage currents that are enhanced by offset voltages. A higher level input signal applied to such input structure tends to exhibit better noise immunity than low level input signals. However, such higher level input signals are generally too great for charge transfer devices, in that the potential wells become saturated with charge. In my copending application, Ser. No. 953,809, filed on Oct. 23, 1978 which is incorporated herein by reference, there is described an improved charge transfer device that has an input portion structured so that a distinct predetermined fraction of the signal input current is directed to the adjacent or first potential well of the device. Also, such charge transfer device has a signal input portion that includes a bi-polar transistor where the channel in which the potential well or wells resides is the virtual collector of such input structure. In a more specific manner, the charge transfer device of my copending application describes an input portion that includes an injection transistor and at least one partitioning transistor. The bases or gates of the injection and partitioning transistors are common. The collector or drain of the injection transistor is structured to form a part of the potential well channel. For high-speed operation and to provide noise immunity, one or more partitioning transistors are provided where the collector or drain of the partitioning transistor or transistors, as the case may be, which is separated from the charge packet channel or collector of the first transistor, is connected to a DC source in common with the common bases. The input signal is applied to the commonly connected emitters of the injection and partitioning transistors; and the total base emitter junction area of the injection transistor is smaller than the total base emitter junction of the partitioning transistor or transistors in proportion to the fraction of the input signal that is to be directed to the adjacent potential well. This signal input structure enhances the input of high frequency signals and the signal-to-noise ratio of the input signal. Also, the signal input portion involves only a single step without additional input clocking circuits in order to maximize the bandwidth of the input signal. Thus, with such a structure, the input signal level may be sufficiently high to provide better noise immunity and the current level may be sufficiently low for the metering of charge packets for coupling or injection into the transfer or shift register portion of the device.
It may be desirable, however, for some applications to operate the charge transfer device by continuously injecting signal current therein, or by changing the clocking speed of the CTD. Under such conditions, a phenomena may occur, where the signal current, in effect overflows and spreads into adjacent potential wells. Such spreading is commonly referred to as "blooming". Blooming occurs if the signal exceeds the charge handling capacity of the potential wells of the device.
Thus, it is desirable to provide a high speed input structure for a charge transfer device that permits a high input signal level, and yet prevents "blooming" in applications where the signal exceeds the capacity of a potential well.